1. Field of the Invention
The present invention relates to a semiconductor memory such as a dynamic random access memory (DRAM).
2. Description of Related Art
Japanese Unexamined Patent Publication No. 2003-151276 discloses an example of conventional semiconductor memories (paragraphs [0020]-[0036], FIG. 4A). The disclosed semiconductor memory is provided with a circuit including global data lines 40A and 40B connected to a local data line connected to a memory core through a switching unit 620 made of a transfer gate. During a precharge period, the global data lines 40A and 40B are connected to a precharge power supply whose potential is half of external power supply voltage VDD(VDD/2).
In the conventional structure described above, the following problem arises when the H level potential of the local data line during reading is set equal to the H level potential of the global data lines 40A and 40B during writing.
Here, the H level potential of the local data line during reading and the H level potential of the global data lines 40A and 40B during writing are represented as voltage VDD and their L level potentials as voltage GND (0V).
In a reading operation, the potential of the global data lines 40A and 40B on the L side is the voltage GND, while that on the H side is increased only to VDD−Vt, which is a potential lower than the voltage VDD by threshold voltage Vt of the transistor forming the switching unit 620. Therefore, an average potential of the global data lines 40A and 40B is 0.5×(VDD−Vt).
In a writing operation, the potential of the global data lines 40A and 40B on the H side is the voltage VDD and that on the L side is the voltage GND. Therefore, an average potential of the global data lines 40A and 40B is 0.5×VDD.
In such a case, the average potential of the global data lines 40A and 40B in the reading operation varies from that in the writing operation. Therefore, in the conventional structure which is configured to apply constant voltage from a certain voltage generator at all times during the precharge period, electric current flows at least in the precharge period after the reading or writing, thereby consuming power. To be more specific, when the potential of the precharge power supply is 0.5×(VDD−Vt), which is the same as the average potential of the global data lines 40A and 40B during reading, a potential difference occurs and the current flow because the average potential of the global data lines 40A and 40B at the beginning of the precharge period after the writing is 0.5×VDD. On the other hand, when the potential of the precharge power supply is 0.5×VDD, which is the same as the average potential of the global data lines 40A and 40B during writing, a potential difference occurs and the current flows because the average potential of the global data lines 40A and 40B at the beginning of the precharge period after the reading is 0.5×(VDD−Vt). In general, a semiconductor memory includes about 1,000 precharge circuits. Therefore, if the current flows as described above during the precharge period, power consumption by the semiconductor memory is increased.